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true bipolar input, dual 12 - bit/14 -bit, 2- channel, simultaneous sampling sar adc AD7366/ad7367 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 - 2010 analog devices, inc. all rights reserved. f eatures dual 12 - bit/14 - bit , 2- channel adc true b ipolar a nalog i nputs pro grammable i nput r anges : 10 v , 5 v , 0 v to 10 v 12 v with 3 v external reference throughput rate: 1 msps simultaneous conversion with read in less than 1 s high analog input impeda nce low current consumption : 8.3 ma typical in n ormal mode 320 na typical in s hutdown mode AD7366 72 db snr at 50 khz input frequency 12- bit n o m issing c odes ad7367 76 db snr at 50 khz input frequency 14- bit n o m issing c odes accurate o n- chip reference: 2. 5 v 0.2% ? 40 c to +8 5 c operation high speed serial interface c ompatible with spi ?, qspi? , microwire? , and dsp i cmos ? p rocess t echnology available in a 24 -l ead tssop f unctional b lock d iagram 12-/14-bit successive approxima tion adc d out a output drivers contro l logic t/h buf v a1 v a2 mux ref AD7366/ad7367 v drive d cap a av cc dv cc buf d out b output drivers 12-/14-bit successive approxima tion adc t/h v b1 v b2 agnd agnd v ss dgnd d cap b cs sclk cnvst bus y addr range0 range1 refsel mux v dd 06703-001 figure 1. g eneral d escription the ad73 66/ ad736 7 1 the AD7366/ad7367 are fabricated on the analog devices , inc ., industrial cmos process ( i cmos are dual 12- bit /14 - bit , high speed, low power, successive approximation analog - to - digital converters ( adc s) that feature throughput ra tes up to 1 msps. the device contain s two adcs, each preceded by a 2 - channel multiplexer, and a low no ise, wide bandwid th track - and - hold amplifier. 2 the AD7366/ad7367 have an on - chip 2.5 v reference that can be disabled to allow the use of an external reference. if a 3 v reference is applied to the d cap a and d cap b pins, the a d7366/ ad7367 can accept a true bipolar 12 v analog input. minimum 12 v v dd and v ss su pplies are required for the 12 v input range. ), which is a technology platform combining the advantage s of low and high voltage cmos. the i cmos process allows the AD7366/ad7367 t o accept high voltage bipolar signals in addition to reducing power consumption and package size. the AD7366/ad7367 can accept true bipolar analog input signals in the 10 v range, 5 v range , and 0 v to 10 v range. product highlights 1. the AD7366/ad7367 can accept true bipolar analog input signals, as well as 10 v, 5 v, 12 v (with external refer - ence) , and 0 v to 10 v unipolar signals. 2. two complete adc functions allow simultaneous sampling and co nversion of two channels. 3. 1 msps serial interface : spi - /qspi - /dsp - /microwire - compatible interface. table 1. related products device resolution throughput rate number of channels AD7366 12- bit 1 msps dual, 2 - channel AD7366 -5 12-bi t 500 ksps dual, 2 - channel ad7367 14- bit 1 msps dual, 2 - channel ad7367 -5 14- bit 500 ksps dual, 2 - channel 1 protected by u.s. patent no. 6,731,232 . 2 i cmos process technology. for analog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher voltage levels, i cmos is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance .
important links for the AD7366_7367 * last content update 12/15/2013 09:37 pm documentation cn-0042: driving the AD7366/ad7367 bipolar sar adc in low- distortion dc-coupled ug-408: evaluating the AD7366/ad7367 ms-2210: designing power supplies for high speed adc ics for programmable logic control and distributed control systems design tools, models, drivers & software bemicro fpga project for AD7366 with nios driver bemicro fpga project for ad7367 with nios driver evaluation kits & symbols & footprints view the evaluation boards and kits page for the AD7366 view the evaluation boards and kits page for the ad7367 symbols and footprints for ad-7366 symbols and footprints for ad-7367 product recommendations & reference designs cn-0042: driving the AD7366/ad7367 bipolar sar adc in low- distortion dc-coupled design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data similar products & parametric selection tables find similar products by operating parameters suggested companion products recommended input driver amplifiers for either the AD7366/ad7367 (for both AD7366 and ad7367) for high speed, low power, low cost in single ended applications, we recommend the ad8021, ad8031 or the ada4899-1 . (for the AD7366) for wideband, low distortion, high output current, we recommend the ad8022 or the ad797 . (for the AD7366) for low distortion, fast settling, we recommend the ad8597 or the dual ad8599 . (for the AD7366) for precision, low offset, low bias current, jfet amplifiers, we recommend the ad8610 or ada4627-1 . (for the ad7367) for lower frequency applications, we recommend the ad8597 or the ada4627 . recommended precison references - 2.5v - 3.0v for the AD7366/ad7367 for high output current applications, we recommend the adr431 or the ref193 . for wide supply applications, we recommend the ad780 . for cost sensitive applications, we suggest the ad1582 or the adr391 . (for the AD7366) for applications requiring the lowest noise performance and output trim adjust, we recommend the adr441 . recommended voltage regulators for the ad7367 for low dropout regulators with inputs up to 5v, we recommend the low noise adp151 or the low power adp160 . for high current switching regulators with inputs up to 5v, we recommend the low noise adp2114 . recommended power solutions for selecting voltage regulator products, use adisimpower . for selecting supervisor products, use the supervisor parametric search . sample & buy AD7366 ad7367 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
AD7366/ad7367 rev. d | page 2 of 28 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 11 terminology .................................................................................... 14 theory of operation ...................................................................... 16 circuit information .................................................................... 16 converter operation .................................................................. 16 analog inputs .............................................................................. 16 transfer function ....................................................................... 17 typical connection diagram ................................................... 18 driver amplifier choice ........................................................... 19 reference ..................................................................................... 19 modes of operation ....................................................................... 20 normal mode .............................................................................. 20 shutdown mode ......................................................................... 21 power - up times ......................................................................... 21 serial interface ................................................................................ 22 microprocessor interfacing ........................................................... 24 AD7366/ad7367 to adsp - 218x .............................................. 24 AD7366/ad7367 to adsp - bf53x ........................................... 24 AD7366/ad7367 to tms320vc5506 ..................................... 25 AD7366/ad7367 to dsp563xx ................................................ 25 appl ication hints ........................................................................... 27 layout and grounding .............................................................. 27 outline dimensions ....................................................................... 28 o rdering guide .......................................................................... 28 revision history 11 /10 rev. c to rev. d changes to d out a and d out b description in table 6 ................. 9 changes to serial interface section .............................................. 22 changes to figure 27 ...................................................................... 23 10 /10 rev. b to rev. c changes to d out a and d out b description in table 6 ................. 9 changes to serial interface section .............................................. 22 changes to figure 27 ...................................................................... 23 8 /0 9 rev. a to rev. b changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 6 9/07 rev. 0 to rev. a changes to title ............................................................................... 1 changes to specifications ................................................................ 3 changes to figure 5 ........................................................................ 11 changes to terminology section .................................................. 14 changes to figure 20 ...................................................................... 18 changes to figure 28 ...................................................................... 23 updated outline dimensions ....................................................... 28 changes to ordering guide .......................................................... 28 5 /0 7 rev ision 0: initial version
AD7366/ad7367 rev. d | page 3 of 28 specifications av cc = dv cc = 4. 7 5 v to 5. 2 5 v, v dd = 11.5 v to 16 .5 v, v ss = ? 16 .5 v to ?11.5 v, v drive = 2.7 v to 5.25 v, f s = 1.12 msps, f sclk = 48 mhz, v ref = 2.5 v i nternal/ e xternal , t a = ? 40c to +85c, unless otherwise noted . table 2 . AD7366 parameter min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal -to - noise ratio (snr) 1 70 72 db signal -to - noise + distortion ratio (sinad ) 1 70 71 db total harmonic distortion (thd) 1 ? 85 ?78 db spurious - free dynamic range (sfdr) ? 87 ?78 db intermodulation distortion (imd) 1 fa = 49 khz, fb = 51 khz second - order terms ? 88 db thir d- order terms ? 88 db channel - to - channel isolation 1 ? 90 db sample and hold aperture delay 2 10 ns aperture jitter 2 40 ps aperture delay matching 2 100 ps full power bandwidth 35 mhz @ 3 db, 10 v range 8 mhz @ 0.1 db, 10 v range dc accuracy resolution 12 bits integral nonlinearity (inl) 1 0.5 1 lsb differential nonlinearity (dnl) 1 0.25 0.5 lsb guaranteed no m issed codes to 12 bits positive full - scale error 1 1 7 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range positive full - scale error match 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel - to - channel matching for adc a and adc b zero code error 1 0.5 3 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range zero code error mat ch 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel - to - channel matching for adc a and adc b negative full - scale error 1 1 7 lsb 5 v and 10 v analog input range 1 6 lsb 0 v to 10 v analog input range negative full - scale error match 1 1.5 lsb matching from adc a to adc b 0.1 lsb channel - to - channel matching for adc a and adc b analog input input voltage ranges pr ogrammed via range pins; see table 8 10 v 5 v 0 to 10 v dc leakage current 0.01 1 a input capacitance 9 pf when in track, 10 v range 13 pf when in track, 5 v and 0 v to 10 v range input impedan ce 260 k 10 v @ 1 msps 2.5 m 10 v @ 100 k sps 125 k 5 v and 0 v to 10 v range @ 1 msps 1.2 m 5 v and 0 v to 10 v range @ 100 ksps
AD7366/ad7367 rev. d | page 4 of 28 parameter min typ max unit test conditions/comments reference input/output reference output voltage 3 2.495 2.5 2.505 v 0.2% max @ 25c long - term st ability 150 ppm 1000 hours output voltage hysteresis 1 50 ppm reference input voltage range 2.5 3.0 v dc leakage current 0.01 1 a external reference applied to pin d cap a/ pin d cap b input capacitance 25 pf 5 v and 10 v analog input range 17 pf 0 v to 10 v analog input range d cap a, d cap b output impedance 7 reference temperature coefficient 6 25 ppm/c v ref noise 20 v rms bandwidth = 3 k hz logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.8 v input current, i in 0.01 1 a v in = 0 v or v drive input c apacitance, c in 2 6 pf logic outputs output high voltage, v oh v drive ? 0.2 v output low voltage, v ol 0.4 v floating state leakage current 0.01 1 a floating state output capacitance 2 8 pf conversion rate conversion time 610 ns track/hold acquisition time 2 140 ns full - scale step input throughput rate 1.12 msps 4.75 v v drive 5.25 v, f sclk = 48 mhz 1 msps 2.7 v v drive < 4.75 v, f sclk = 35 mhz power requirements digital i nputs = 0 v or v drive v cc 4.75 5.25 v see table 7 v dd +11.5 +16.5 v see table 7 v ss ?16.5 ?11.5 v se e table 7 v drive 2.7 5.25 v normal mode (static) i dd 370 550 a v dd = +16.5 v i ss 40 60 a v ss = ?16.5 v i cc 1.5 2.25 ma v cc = 5.5 v normal mode (operational) f s = 1.12 msps i dd 1.8 2.0 ma v dd = +16.5 v i ss 1.5 1.6 ma v ss = ?16.5 v i cc 5 5.6 5 ma v cc = 5.25 v, internal reference enabled shutdown mode i dd 0.01 1 a v dd = +16.5 v i ss 0.01 1 a v ss = ?16.5 v i cc 0.3 3 a v cc = 5.25 v power dissipation normal mode (operation al) 89.1 mw v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v, f s = 1.12 msps 50 mw 10 v input range, f s = 1.12 msps 70 mw 5 v and 0 v to 10 v input range, f s = 1.12 msps shutdown mode 1.9 48.75 w v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 see the terminology se ction. 2 samp le tested during initial release to ensure compliance. 3 refers to pin d cap a or pin d cap b spec ified for 25 o c.
AD7366/ad7367 rev. d | page 5 of 28 av cc = dv cc = 4. 7 5 v to 5. 2 5 v, v dd = 11.5 v to 16 .5 v, v ss = ? 16.5 v to ? 11.5 v, v drive = 2.7 v to 5.25 v, f s = 1 msps, f sclk = 48 mhz, v ref = 2.5 v i nternal/ e xternal , t a = ? 40 c to +85c, unless otherwise noted . table 3 . ad7367 parameter min typ max unit test conditions/comments dynamic performance f in = 50 khz sine wave signal -to - noise ratio (snr) 1 74 76 db signal -to - noise + distortion rati o (sinad) 1 73 75 db total harmonic distortion (t hd) 1 ?84 ? 78 db spurious - free dynamic range (sfdr) ?87 ? 79 db intermodulation distortion (imd) 1 fa = 49 khz, fb = 51 khz second - order terms ? 91 db third - order terms ? 89 db channel - to - channel isolation 1 ? 90 db sample and hold aperture delay 2 10 ns aperture jitter 2 40 ps aperture delay matching 2 100 ps full power bandwidth 35 mhz @ 3 db , 1 0 v range 8 mhz @ 0.1 d b, 1 0 v range dc accuracy resolution 14 bits integral nonlinearity (inl) 1 2 3.5 lsb differential nonlinearity (dnl) 1 0. 5 0.90 lsb guaranteed no m issed codes to 14 bits positive full - scale error 1 4 20 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v analog input range positive full - scale error match 1 3 lsb matchin g from adc a to adc b 0.2 lsb channel - to - channel matching for adc a and adc b zero code error 1 1 10 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v analog input range zero code error match 1 3 lsb matching from adc a to adc b 0.2 lsb channel - to - channel matching for adc a and adc b negative full - scale error 1 4 20 lsb 5 v and 10 v analog input range 5 20 lsb 0 v to 10 v ana log input range negative full - scale error match 1 3 lsb matching from adc a to adc b 0.2 lsb channel - to - channel matching for adc a and adc b analog input input voltage ranges programmed via range pins; see table 8 10 v 5 v 0 to 10 v dc leakage current 0.01 1 a input capacitance 9 pf when in track , 1 0 v range 13 pf when in track , 5 v and 0 v to 10 v range input impedance 260 k 10 v @ 1 msps 2.5 m 10 v @ 100 k sps 125 k 5 v and 0 v to 10 v range @ 1 msps 1.2 m 5 v and 0 v to 10 v range @ 100 ksps
AD7366/ad7367 rev. d | page 6 of 28 parameter min typ max unit test conditions/comments reference input/output reference output voltage 3 2.495 2.5 2.505 v 0.2% max @ 25c long - term stability 1 50 ppm 1 000 hours output voltage hysteresis 1 50 ppm reference input voltage range 2.5 3.0 v dc leakage current 0.01 1 a external reference applied to pin d cap a/pin d cap b input capacitance 25 pf 5 v and 10 v analog input range 17 pf 0 v to 10 v analog input range d cap a, d cap b output impedance 7 reference temperature coefficient 6 25 ppm/c v ref noise 20 v rms bandwidth = 3 k hz logic inputs input high voltage, v inh 0.7 v drive v input low voltage, v inl 0.8 v input current, i in 0.01 1 a v in = 0 v or v drive input c apacitance, c in 2 6 pf logic outputs output high voltage, v oh v drive ? 0.2 v output low voltage, v ol 0.4 v floating state leakage current 0.01 1 a floating state output capacitance 2 8 pf conversion rate conversion time 680 ns track/hold acquisition time 2 140 ns full - scale step input throughput rate 1 msps 4.75 v v drive 5.25 v, f sclk = 48 mhz 900 ksps 2.7 v v drive < 4.75 v, f sclk = 35 mhz power requirements digital i nputs = 0 v or v drive v cc 4.75 5.25 v see table 7 v dd + 11.5 +16.5 v see table 7 v ss ? 16.5 ?11.5 v see tabl e 7 v drive 2.7 5.25 v normal mode (static) i dd 370 550 a v dd = +16. 5 v i ss 40 60 a v ss = ?16. 5 v i cc 1.5 2.25 ma v cc = 5. 5 v normal mode (operational) f s = 1 msps i dd 1.8 2.0 m a v dd = +16.5 v i ss 1.5 1.6 m a v ss = ?1 6. 5 v i cc 5 5. 65 ma v cc = 5.2 5 v , internal reference enabled shutd own mode i dd 0.01 1 a v dd = +16. 5 v i ss 0.01 1 a v ss = ?16. 5 v i cc 0.3 3 a v cc = 5.2 5 v power dissipation normal mode (operational) 80.7 89.1 mw v dd = +16. 5 v, v ss = ?16.5 v, v cc = 5.25 v 50 mw 10 v input range, f s = 1 msps 70 mw 5 v and 0 v to 10 v input range, f s = 1 msps shutdown mode 1.9 48.75 w v dd = +16.5 v, v ss = ?16.5 v, v cc = 5.25 v 1 see the terminology section. 2 sample tested during initial release to ensure compliance. 3 refers to pin d cap a or pin d cap b spec i fied for 25 o c.
AD7366/ad7367 rev. d | page 7 of 28 timing specification s av cc = dv cc = 4. 7 5 v to 5. 2 5 v , v dd = 11.5 v to 16 .5 v, v ss = ?16.5 v to ?11 .5 v, v drive = 2.7 v to 5.25 v, t a = ? 40c to +85c, unless otherwise noted . 1 table 4 . parameter limit at t min , t max unit test conditions/ comments 2.7 v v drive < 4.75 v 4.75 v v d rive 5.25 v t convert conversion ti me, i nternal clock; cnvst falling edge to busy falling edge 680 680 ns max ad7367 610 6 10 ns max AD7366 f sclk 10 10 k hz min frequency of serial read clock 35 48 mhz max t quiet 30 30 ns m in minimum quiet time required between the end of serial read and the start of the next conversion t 1 10 10 ns min minimum cnvst low pulse t 2 40 40 ns min cnvst fall ing edge to busy rising edge t 3 0 0 ns min busy fa lling edge to msb , valid when cs is low for t 4 prior to busy going l ow t 4 10 10 ns max delay from cs falling edge until pin 1 (d out a) and pin 23 (d out b) are three - state disabled t 5 2 20 14 ns max data access time after sclk falling edge t 6 7 7 ns min sclk to data valid hold time t 7 0.3 t sclk 0.3 t sclk ns min sclk low pulse width t 8 0.3 t sclk 0.3 t sclk ns min sclk high pulse width t 9 10 10 ns max cs rising edge to d out a, d out b, hi gh impedanc e t power - up 70 70 s max power - up time from shutdown mode ; time required between cnvst rising edge and cnvst falling edge 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. all timing specifications are with a 25 pf load capacitance. with a load capacitance greater than 25 pf, a digital buffer or latch must be used. see the terminology section, figure 25 , and figure 26 . 2 th e time required for the output to cross is 0.4 v or 2.4 v.
AD7366/ad7367 rev. d | page 8 of 28 absolute maximum rat ings table 5. parameter rating v dd to agnd , dg nd ? 0.3 v to +16.5 v v ss to agnd, dgnd ?16.5 v to +0.3 v v drive to dgnd ? 0.3 v to dv cc v dd to av cc (v cc ? 0.3 v) to +16.5 v av cc to agnd, dgnd ? 0.3 v to +7 v dv cc to av cc ? 0.3 v to +0.3 v dv cc to dgnd ? 0.3 v to +7 v v drive to agnd ? 0.3 v to d v cc ag nd to dgnd ? 0.3 v to +0.3 v analog input voltage to agnd v ss ? 0.3 v to v dd + 0.3 v digital input voltage to dgnd ? 0.3 v to v drive + 0.3 v digital output voltage to gnd ? 0.3 v to v drive + 0.3 v d cap a , d cap b i nput to agnd ? 0.3 v to a v cc + 0.3 v input c urrent to any pin except supplies 1 10 ma operating temperature range ? 40c to +8 5c storage temperature range ? 65c to +150c junction temperature 150c tssop package ja thermal impedance 128 c/w jc thermal impedance 42c/w pb -f ree temperature, soldering reflow 260c esd 1.5 kv 1 transient currents of up to 100 ma will not cause latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of t he device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
AD7366/ad7367 rev. d | page 9 of 28 pin configuration and function descriptions d out a 1 2 3 addr 4 dgnd 24 23 bus y 22 cnvst 21 range0 5 range1 6 agnd 7 sclk 20 cs 19 refsel 18 8 agnd 17 9 16 10 15 11 14 12 13 AD7366/ ad7367 top view ( not to scale) d out b d cap a d cap b dv cc av cc v ss v a1 v a2 v b1 v b2 v dd v drive 06703-002 figure 2. pin configuration table 6 . pin function descriptions pin no. mnemonic description 1, 23 d out a, d out b serial data outputs. the data output is supplied to each pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input; 12 sclk cycles are required to access a result from the AD7366, and 14 sclk cycles are required for the ad7367. the data simultaneously appears on both pins from t he simultaneous con - versions of both adcs. the data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits for the ad7367 and is provided msb first. if cs is held low for a further 14 sclk cycles, on either d out a or d out b, the data from the other adc follows on that d out pin. note, the second serial result from the ad 7366 is preceeded by two zeros. therfore data from a simultaneous conversion on both adcs can be gathered in serial format on either d out a or d out b using only one serial port. see the serial interface section for more information. 2 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface operate s. this pin should be decoupled to dgnd. the voltage range on this pin is 2.7 v to 5.25 v and may be different from the voltage at a v cc and dv cc , but should never exceed either by more than 0.3 v. to achieve a throughput rate o f 1.12 msps for the AD7366 or 1 msps for the ad7367, v drive must be 4.75 v. 3 dv cc digital supply voltage, 4.75 v to 5.25 v. the dv cc and av cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage d iffere nce between them never exceed s 0.3 v even on a transient basis. this suppl y should be decouple d to dgnd. place 10 f and 100 nf decoupling capacitors on the dv cc pin. 4, 5 range1, range0 analog input range selection, logic i nputs. the polarity on these pins determines the input range of the analog input channels. see the analog inputs section and table 8 for details . 6 addr multiplexer select, logic i nput . thi s input is used to select the pair of cha nnels to be simultaneously converted, either channel 1 of both adc a and adc b, or channel 2 of both adc a and adc b. the logic state on this pin is latched on the rising edge of busy to set up the multiplexer for the next conversion. 7, 17 agnd analog gr ound. ground reference point for all analog circuitry on the AD7366/ad7367 . all analog input signals and any external reference signal should be referred to this agnd voltage. both agnd pins should connect to the agnd plane of a system. the agnd and dgnd v oltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 8 av cc analog supply voltage, 4.75 v to 5.25 v. this is the supply voltage for the adc cores. the av cc and dv cc voltages should ideally be at the same potential. for best performance, it is recommended that the dv cc and av cc pins be shorted together, to ensure that the voltage difference between them never exceed s 0.3 v even on a transient basis. this supply should be decoupled to agnd. place 1 0 f and 100 nf decoupling capacitors on the av cc pin . 9, 16 d cap a, d cap b decoupling c apacitor pins. decoupling capacitors are connected to these pins to decouple the reference buffer for each respective adc. for best performance , it is recommended that a 680 nf decoupling capacitor be used on these pins. provided the output is buffered, t he on- chip reference can be taken from these pins and applied ext ernally to the rest of a system . 10 v ss negative power supply voltage . this is the ne gative supply volt age for the high voltage a nalog i nput structure of the AD7366/ad7367 . the supply must be l ess than a maximum voltage of ? 11.5 v for all analog input ranges. see table 7 for more details. place 10 f and 100 nf decoupling capacitor s on the v ss pin. 11, 12 v a1 , v a2 analog inputs of adc a. both analog inputs are single - ended. the a nalog input range on these channels is determined by the range0 and range1 pins. 13, 14 v b2 , v b1 analog inputs of adc b. both analog inputs are single - end ed. the a nalog input range on these channels is determined by the range0 and range1 pins. 15 v dd positive power supply voltage . this is the positive supply voltage for the high voltage analog i nput structure of the AD7366/ad7367 . the supply must b e greate r than a minimum voltage of 11.5 v for all analog input ranges. see table 7 for more details. place 10 f and 100 nf decoupling capacitors on the v dd pin.
AD7366/ad7367 rev. d | page 10 of 28 pin no. mnemonic description 18 refsel internal/external reference selection , logic in put. if this pin is tied to logic high, the on - chip 2.5 v reference is used as the reference source for both adc a and adc b. in addition, pin d cap a and pin d cap b must be tied to decoupling capacitors. if the refse l pin is tied to gnd, an external refer ence can be supplied to the AD7366/ ad7367 through the d cap a pin, the d cap b pin , or both pin s. 19 cs chip select, active low logic input . this input frames the serial data transfer . when cs is logic low , the output bus is enabled and the c onversion result is output on d out a and d out b . 20 sclk serial clock , logic i nput. a serial clock input provides the sclk for accessing the data from the AD7366/ad7367 . 21 c nv st conversion start , logic input . this pin is edge triggered. on the falling edge of this input, the track/hold goes into hold mode and the conversion is initiated. if c nv st is low at the end of a conversion, the part goes into power - down mode. in this case, the rising edge of c nv st instruct s the part to power up again . 22 busy b usy output. busy transitions high when a conversion is started and remains high until the conversion is complete. 24 dgnd digital ground. g round reference point for a ll digital circuitry on the AD7366/ad7367 . the dgnd pin should connect to the dgnd plane of a system. the dgnd and agnd voltages should ideally be at the same potential and must not be more than 0.3 v apart, even on a transient basis.
AD7366/ad7367 rev. d | page 11 of 28 typical performance characteristics t a = 25c, unless o therwise noted. 16000 14000 12000 10000 8000 6000 4000 2000 0 dnl error (lsb) code av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps t a = 25c internal reference ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 06703-003 figure 3 . ad7367 typical dnl 16000 14000 12000 10000 8000 6000 4000 2000 0 inl error (lsb) code av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps t a = 25c internal reference ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 06703-004 figure 4 . ad7367 typical inl ?20 0 ?40 ?60 ?80 ?100 ?120 ?140 ?160 (db) frequency (khz) 500 0 50 100 150 200 250 300 350 400 450 06703-005 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps, f in = 50khz internal reference snr = 76db, sinad = 75db figure 5 . ad7367 fft ?76 ?78 ?80 ?86 ?84 ?82 10 100 1000 thd (db) analog input frequency (khz) 10v range 5v range 0v to 10v range 06703-006 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference figure 6 . thd vs. analog input frequency ?66 ?81 ?76 ?71 ?86 10 100 1000 thd (db) analog input frequency (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 5v range r in = 5100 r in = 3000 r in = 3900 r in = 470 r in = 2000 r in = 1300 r in = 240 r in = 56 06703-007 figure 7 . thd vs. analog input frequency for various source impedances 77 69 71 73 75 67 10 100 1000 sinad (db) analog input frequency (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 10v range 06703-008 0v to 10v range 5v range figure 8 . sinad vs. analog input frequency
AD7366/ad7367 rev. d | page 12 of 28 ?70 ?85 ?80 ?75 ?90 ?95 ?100 ?105 ?110 0 100 200 300 400 500 600 channel-to-channel isolation (db) frequency of input noise (khz) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 0v to 10v range 5v range 10v range 06703-009 figure 9 . channel -to- channel isolation 31 codes 344 codes 8191 8192 8193 8196 8195 8194 code 06703-010 0 10000 20000 30000 40000 50000 60000 70000 80000 90000 100000 110000 106091 codes figure 10 . histogram of codes for 200k samples ?70 ?80 ?90 ?100 ?110 ?120 0 200 400 1200 1000 800 600 psrr (db) supply ripple frequency (khz) v cc , adc a v dd, adc b v dd , adc a v cc , adc b 100mv p-p sine wave on av cc no decoupling capacitor v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps v ss , adc a 06703-011 v ss , adc b figure 11 . psrr vs. supply ripple frequency without supply decoupling 80 60 40 20 0 ?20 ?40 100 200 300 400 500 600 700 800 900 1000 analog input current (a) throughput rate (ksps) v in = 0v to 10v v in = +5v v in = +10v v in = ?5v v in = ?10v av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 06703-012 figure 12 . analog input current vs. throughput rate 2.5050 2.5025 2.5030 2.5035 2.5040 2.5045 2.5020 2.5015 2.5010 2.5005 2.5000 0 10 20 30 40 50 60 70 80 v ref (v) current load (a) av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v 06703-013 figure 13 . v ref vs. reference output current drive 0.250 0.300 0.200 0.150 0.100 0.50 0 0 500 1000 1500 2000 2500 v out or v cc ? v out (v) current (a) 06703-014 sink current source current av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v, f s = 1msps internal reference figure 14 . d out source current vs. (v cc ? v out ) and d out sink current vs. v out
AD7366/ad7367 rev. d | page 13 of 28 power (mv) sampling frequency (ksps) 100 400300200 600500 700 800 900 1000 15 25 35 45 55 65 av cc = 5v, dv cc = 5v v dd = 15v, v ss = ?15v v drive = 3v f s = 1msps internal reference 0v to 10v range 5v range 10v range 06703-017 figure 15 . power vs. sampling frequency in normal mode
AD7366/ad7367 rev. d | page 14 of 28 terminology differential nonlinearity (dnl) d nl is t he difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale , a point 1 lsb below the first code transition , and full scale , a point 1 lsb above the last code transition. zero code error t he deviation of the mid scale trans ition (all 1s to all 0s) from the ideal v in voltage, that is , agnd ? ? lsb for bipolar ranges and 2 v ref ? 1 lsb for the unipolar range. positive full - scale error t he deviation of the last code transition (011110) to (011111) from the ideal ( that is, +4 v ref ? 1 lsb or +2 v ref C 1 lsb) after the zero code error has been factor ed out. negative fu ll - scale error the deviation of the first code transition (10000) to (10001) from the ideal ( that is, ? 4 v ref + 1 lsb, ? 2 v ref + 1 lsb , or agnd + 1 l sb) after the zero code error has been factored out . zero code error match the difference in zero code error across all channels. positive full - scale error match the difference in positive full - scale error across all channels. negative full - scale error ma tch t he difference in negative full - scale error across all channels. track - and - hold acquisition time the track - and - hold ampli fier returns to track mode at the end of a conversion. track - and - hold acquisition time is the time required for the output of the t rack - and - hold amplifier to reach its final value, within ? ls b, after the end of a conversion. signal -to - noise ( + distortion) ratio (s in ad ) this ratio is t he measured ratio of signal - to - noise ( + dis tortion) at the output of the adc . the signal is the rms amplitude of the fundament al. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza - tion process : the more levels, the smaller the quantization n oise. the theoretical signal -to - noise ( + distortion) ratio for an ideal n- bit converter with a sine wave input is as follows : signal- to - noise ( + distortion) = ( 6.02 n + 1.76 ) db thus , for a 12 - bit converter, th e sinad is 74 db. total harmonic distortion (thd) t hd is the ratio of the rms sum of harmonics to the fundamental. for the AD7366/ad7367 , thd is defined as follows : 1 65432 v vvvvv thd 22222 log20) db ( ++++ = w here : v 1 is the r ms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes o f the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic , or spurious noise , is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 , excluding dc) to the rms value of the fundament al. normally, the value of this specification is determined by the la rgest harmonic in the spectrum. however, for adcs where the harmonics are buried in the noise floor, it is a noise peak. channel -to - channel isolation channel - to - channel isolation is a me asure of the level of cross - talk between any two channels when operating in any of the input ranges. it is measure d by applying a full - scale, 150 khz sine wave signal to all unselected input channels and determining how much that signal is attenuated in th e selected channel with a 50 khz signal. the figure given is the typical value across all four channels for the AD7366/ad7367 (s ee figure 9 fo r more information) . intermodulation distortion (imd) with inputs consisting of sin e waves at two frequencies, fa and fb, any active device with nonlinearities create s distortion prod - ucts at the sum, and differen t frequencies of mfa nfb , where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are tho se for which neither m nor n is equal t o zero. for example , the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) , and (fa ? 2fb). the AD7366/ad7367 are tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second - order t erms are usually distanced in frequency from the original sine waves , and the third - order terms are usually at a frequency close to the input frequencies. as a result, the second - and third - order terms are specified separately. the calculation of the inter modulation distortion is as per the thd specification , where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels .
AD7366/ad7367 rev. d | page 15 of 28 power supply rejection ratio (psrr ) variations in power supply affect the full - scale transition but not the converters linearity. psr r is the maximum change in the full- scale transition point due to a change i n power supply voltage from the nominal value (see figure 11 ). thermal ( or output voltage) hysteresis thermal (o r o utput voltage) hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either t_hys+ = +25c to t max to +25c or t_hys ? = +25c to t min to +25c it is expressed in ppm using the following equation: 6 10 )c25( )_()c25( ) ppm ( ? = ref ref ref hys v hys tv v v where: v ref (25c) is v ref at 25c. v ref (t_hys) is the maximum change of v ref at t_hys+ or t_hys ?.
AD7366/ad7367 rev. d | page 16 of 28 theory of operation circuit information the ad73 66/ad7367 are fast, dual, 2 -c hannel, 1 2- /14 - bit, bipolar input, simultaneous sampling, serial a dcs . the AD7366/ad7367 can accept bipolar input ranges of 10 v and 5 v. they can also accept a unipolar input range of 0 v to 10 v . the AD7366/ad7367 require v dd and v ss dual supplies for the high voltage analog input structure s . these supplies must be equal to or greater than 11.5 v. see table 7 for the minimum requirements on these supplies for each analog input range . the ad73 66/ad7367 require a low voltage 4.75 v to 5.25 v a v cc supply to power the adc core. table 7. reference and supply requirements for e ach analog input range selected analog input range (v) reference voltage (v) full - scale input range (v) av cc (v) minimum v dd /v ss (v) 10 2.5 10 5 11.5 3.0 12 5 12 5 2.5 5 5 11.5 3.0 6 5 11.5 0 to 10 2.5 0 to 10 5 11.5 3.0 0 to 12 5 12 the AD7366/ad7367 contain two on - chip , track - and - hold amplifiers, two successive approximation ad cs , and a serial interface with two separate data output pins. the AD7366/ad7367 are available in a 24 - lead tsso p, offering the user considerable space - saving advantages over alternative solutions. the AD7366/ ad7367 require a cnvst signal to start conversion. on the falling edge of cnvst , both track - and -holds are placed into hold mode and the conversions are initiated . the busy signal goes high to indicate that the conversions are taking place. the clock source for eac h suc cessive approximation adc is provided by an interna l oscillator. the busy signal go es low to indicate the end of conversion. on the falling edge of b u sy, the track - and - hold return s to track mode. when the conversion is finished, the serial clock input acc e sses data from the part. the AD7366/ad7367 ha ve an on - chip 2.5 v reference that can be disabled if an external reference is preferred. if the internal reference is to be used elsewhere in a system, the output from d cap a and d cap b must first be buffered. o n power - up , the refsel pin must be tied to either a high or low logic st ate to select either the internal or external reference option . if the internal reference is the preferred option, the user must tie the refsel pin logic high. alternatively, if refsel is tied to gnd then an external reference can be supplied to both adc s through the d cap a and d cap b pins. the analog inputs are configured as two single - ended inputs for each adc. the input voltage range can be selected by programming the range bits as sh own in table 8 . converter operation the AD7366/ad7367 ha ve two successive approximation adc s, each based around two capacitive dacs. figure 16 and figure 17 show simplified sche matics of an adc in acquisition and conversion phase s . the adc comprise s control logic, a sar , and a capacitive dac. in figure 16 (the acquisition phase ), sw2 is closed and sw1 is in p osition a, the comparator is held in a balanc ed condition, and the sampling capacitor arrays acquire the signal on the input. v in agnd a b sw1 sw2 com p ar at or capacitive dac control logic 06703-018 figure 16 . adc acquisition phase when the adc starts a conversion ( see figure 17 ), sw2 opens and sw1 mo ves to p osition b, causing the comparator to become unbalanced. the control logic and the charge redis - tribu tion dac are used to add and subtract fixed amounts of charge fr om the sampling capacitor to bring the comparator back into a balanced condition. when the comparator i s balanced again , the conversion is complete. the control logic generates the adc output code. v in agnd a b sw1 sw2 com p ar at or ca p acitive dac contro l logic 06703-019 figure 17 . adc conversion phase analog inputs each adc in the AD7366/ad7367 has two single- ended analog inputs. figure 18 shows the equivalent circuit of the analog inpu t structure of the AD7366/ad7367 . the two diodes provide esd protection. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward - biased and to start conducting current into the substrate. these diodes can conduct up to 10 ma without causing i rreversible damage to the part. the resistors are lumped components made up of the on resistance of the switche s. the value of these resistors is typically about 170 ?. capacitor c1 can primarily b e attributed to pin capacitance , while c apacitor c2 is the sampling capacitor of the adc . the total lumped capacitance of c1 and c2 is approximately 9 pf for the 10 v input range and approxi - mately 13 pf for all other input ranges.
AD7366/ad7367 rev. d | page 17 of 28 d d v dd c2 r1 v in v ss c1 06703-020 figure 18 . equivalent analog input structure the AD7366/ad7367 can handle true bipolar input voltages. the a nalog input can be set to one of three ranges : 10 v, 5 v, or 0 v to 10 v. the logic levels on p in range0 and p in range1 determine which input range is selected as outlined in table 8 . these range bits should not be changed during the acquisition time prior to a conversion , but can be change d at any other time. table 8 . analog input range selection range1 range0 range selected 0 0 10 v 0 1 5 v 1 0 0 v to 10 v 1 1 do not program the AD7366/ad7367 require v dd and v ss dual supplies for the high voltage analog input structures. these supplies must be equal to or greater than 11.5 v. see table 7 for the require - ments on these supplies. the AD7366/ad7367 require a low voltage 4.75 v to 5.25 v av cc supply to power the adc core, a 4.75 v to 5.25 v dv cc supply for digital p ower , and a 2.7 v to 5.25 v v drive supply for interface power. channel selection is made via the addr pin , as shown in table 9 . the logic level on the addr pin is latched on the rising edge of the busy signal for the next conversion, not the one in progress. when power is first supplied to the AD7366/ad7367 , the default channel selection is v a1 and v b1 . table 9 . channel selection addr channels selected 0 v a1 , v b1 1 v a2 , v b2 transfer function the output coding of the ad 7366/ad7367 is two s complement. the designed code transitions occur at su ccessive integer lsb values (that is, 1 lsb, 2 l sb, and so on). the lsb size is depend en t on the analog input range selected (see table 10 ). the ideal transf er charac teristic is shown in figure 19. table 10 . lsb sizes for each analog input range input range AD7366 ad7367 full - scale range lsb size (mv) full - scale range lsb size (mv) 10 v 20 v/4096 4.88 20 v/16 , 384 1.22 5 v 10 v/4096 2.44 10 v/16 , 384 0.61 0 v to 10 v 10 v/4096 2.44 10 v/16 , 384 0.61 +fsr/2 ? 1lsb analog input 0v adc code 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fsr/2 + 1lsb 06703-021 figure 19 . transfer characteristic track -a nd - hold the trac k- and - hold on the analog input of the AD7366/ ad736 7 allows the adc to accurately convert an input sine wave of full - scale amplit ude to 12 -/ 14- bit accuracy. the input bandwidth of the track - and - hold is greater than the nyquist rate of the adc. t he AD7366/ad7367 can handle frequencies up to 35 mhz. the track - and - hold enters its tracking mode when the busy signal goes low after the cs falling edge. the time required to acquire an input signal depends on how quickly the sampling capacitor is charged. with zero source impedance, 140 ns is suffi - cient to acquire th e signal to the 12- bit level for the AD7366 and the 14- bit level for the ad7367 . the acquisition time f or the 10 v, 5 v, and 0 v to 10 v ranges to settle to within ? lsb is typically 140 ns. the adc returns to hold mode on the falling edge of cnvst . the acquisition time required is calculated using the following formula: t acq = 10 (( r source + r ) c ) where : c is the sampling capacitance. r is the resistance seen by the track - and - hold amplifier looking at the input. r source should inclu de any extra source impedance on the analog input.
AD7366/ad7367 rev. d | page 18 of 28 unlike other bipolar adcs, the AD7366/ad7367 do not have a resistive analog input structure. on the AD7366/ad736 7 , the bipolar analog signal is sampled directly onto the sampling capacitor. this gives t he AD7366/ad7367 high analog input impedance. the analog input impedance can be calculated from the following formula: z = 1/( f s c s ) w here : f s is the sampling frequency. c s is the sampling capacitor value. c s depends on the analog input range chosen (se e the analog inputs section). when operating at 1 msps, the analog input impedance is typically 260 k for the 10 v range. as the sampling frequency is reduced, the analog input impedance further increases. as the analog input impedance increases, the current required to drive the analog input therefore decreases (s ee figure 7 for more information) . typical connection d iagram figure 20 shows a typical c onnection diagram for the AD7366/ ad7367 . in this configuration, the agnd pin is connected to the analog ground plane of the system, and the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the AD7366/ ad7367 accept bipolar s ingle - e nded signals . the AD7366/ad7367 can operate with either an internal or an external reference. in figure 20 , the ad 7366/ ad7367 are configured to operate with the internal 2.5 v reference. a 680 nf decoupling capacitor is required when operating with the internal reference. the av cc and dv cc pin s are connected to a 5 v supply voltage. the v dd and v ss are the dual supp lies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than 11.5 v (see table 7 for more information). the v drive pin is connected to the supply voltage of the microprocessor . the voltage applied to the v drive input controls the voltage of the serial interface. v drive can be set to 3 v o r 5 v. AD7366/ ad7367 microcontroller/ microprocessor cs v drive 1 0f 0.1f + + +3v or +5v supply +11.5v to +16.5v supply ?16.5v to ?11.5v supply +5v supply dv cc av cc busy cnvst refsel v drive d cap a d cap b addr analog inputs 10v, 5v, and 0v to +10v 680nf 680nf sclk d out a d out b dgnd agnd v ss v b1 v b2 v a1 v dd v a2 1 0f 0.1f + + 0.1f + 10f + 0.1f + serial interface 1 0f + 0.1f + + + range1 range0 06703-022 figure 20 . typical connection diagram using internal r eference
AD7366/ad7367 rev. d | page 19 of 28 driver amplifier cho ice the AD7366/ad736 7 have a total of four analog inputs, which operate in single - ended mode. the analog inputs for both adcs can be programmed to one of the three analog input ranges. in applications where the signal source is high impedance, it is recommended that the signa l be buffer ed before applying it to the adc analog inputs. figure 21 shows the configuration of the AD7366/ad7367 in single - ended mode. in applications where the thd and snr are critical specifi - cations, the analog input of the AD7366/ad7367 should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc and can necessitate the use of an input buffer amplifier. when no amplifier is used to drive the analog input, the sour ce impedance should be limited to low values. the maximum source impedance depends on the amount of thd that can be tolerated in the application. the thd increases as the source impedance increases and performance degrades. figure 7 show s thd vs. the analog input frequency for various source impedances. depending on the input range and analog input configuration selected, the AD7366/ad7367 can handl e source impedances as illustrated in figure 7 . due to th e programmable nature of the analog inputs on the AD7366/ad7367 , the choice of op amp used to drive the inputs is a function of the particular application and depends on the analog input voltage range selected. the driver amplifier must be able to settle for a full - scale step to a 14- bit level, 0.0061 %, in less than the specified acquisition time of the AD7366/ad7367 . an op amp such as the ad8021 meets this requirement when operati ng in single - ended mode. the ad8021 needs an external compensating npo type of capacitor. the ad8022 can also be used in high frequency applications where a dual version is required . for lower fre - quency applications, recommended op amps are the ad797 , ad845 , and ad8610 . v+ v? v dd v ss v a1 v cc +5v agnd ad8021 1k? 1k? 15pf c comp = 10pf ?10v/?5v +10v/+5v AD7366/ ad7367* * addit i onal pins omit ted for cl a rity. 10f + 0.1f + 0.1f + + 10f + 06703-023 figure 21 . typical connection diagram with the ad8021 for driving the analog input v drive the AD7366/ad7367 also ha ve a v drive feature to control the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v proc essors. for example, if the AD7366/ad7367 were operated with a v cc of 5 v, t h e v drive pin could be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. thus , the AD7366/ad7367 c an be used with the 10 v input range while still being able to interface to 3 v digital parts. to achieve the maximum throughput rate of 1.12 m sps for the AD7366 or 1 m sps for the ad7367, v drive mus t be greater than or equal to 4.75 v ( see table 2 and table 3 ). the maximum throughput rate with the v drive voltage set to l ess than 4.75 v and greater than 2.7 v is 1 m sps for the AD7366 and 900 ksps fo r the ad7367. reference the AD7366/ad7367 can operate with either the internal 2.5 v on - chip reference or an externally applied reference. the logic state of the refsel pin determines whether the internal refer - ence is used. the internal reference is sele cted for both adc s when the refsel pin is tied to logic high . if the refsel pin is tied to gnd , an external reference can be supplied through the d cap a and d cap b pins. on power - up , the r efsel pin must be tied to either a low or high logic state for the par t to operate. suitable reference sources for the AD7366/ad7367 include the ad780 , ad1582 , adr431 , ref193 , and adr391 . the internal reference cir cuitry consists of a 2.5 v band gap reference and a reference buffer. when operating the AD7366/ ad7367 in internal reference mode, the 2.5 v internal refe rence is available at the d cap a and d cap b pin s, which should be decoupled to agnd using a 680 nf capacitor. it is recom - mended that the internal reference be buffered before applying it elsewhere in the system. the internal reference is capable of sourcing up to 150 a with an analog input range of 10 v and 7 0 a for both the 5 v and 0 v to 10 v ranges . i f the internal reference operation is required for the adc con - version, the refsel pin must be tied to logic high on power - up. the reference buffer requires 70 s to power up and charge the 680 nf decoupling capacitor during the power - up time. the AD7366/ad7367 are specified for a 2.5 v to 3 v reference. when a 3 v reference is selected, the analog input rang es are 12 v, 6 v, and 0 v to 12 v. for these ranges , the v dd supply must be greater than or equal to +12 v and the v ss supply must be less than or equal to ? 12 v.
AD7366/ad7367 rev. d | page 20 of 28 modes of operation the mode of operat ion of the AD7366/ad7367 is selected by the logic state of the cnvst signal at the end of a conver sion. there are two possible modes of operation: normal mode and shut down mode. these modes of operation are designed to provide flexible power management options, which can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. n ormal m ode normal mode is intended for applications that require fast throughput rates . in normal mode, the AD7366/ad7367 remain fully powered at all times, so the user does not need to worry about power - up times. figure 22 shows the general mode of operation of the AD7366 in normal mode ; figure 23 shows normal mode for the ad7367. the conversion is initiated on the falling edge of cnvst as described in the circuit information section. to ensure that the part remains fully powered up at all times, cnvst must be at logic state high before the busy signal go es low. if cnvst is at logic state low when the bu sy signal goes low, the analog circuitry power s down and the part cease s converting. the busy signal remains high for the duration of the conversion. the cs pin must be brought low to bring the data bus out of three -st ate. therefore, 12 sclk cycles are required to read the conversion result from the AD7366 and 14 sclk cycles are r equired to read the conversion result from the ad7367 . the d out line s return to three - state only when cs is brought high. if cs is left low for a n additional 12 sclk cycles for the AD7366 or 14 sclk cycles for the ad7367, the result from t he other on - chip adc is also accessed on the same d out line, as shown in figure 27 and figure 28 (see the serial interface section) . when 24 sclk cycles have elapsed for th e AD7366 or 28 sclk cycles for the ad7367 , the d out line returns to three - state only when cs is brought high , not on the 24 th or 28 th sclk falling edge. if cs is brought high prior to this, the d out line returns to three - state at that point. thus, cs must be brought high when the read is completed, because the bus does not automatically return to three - state upon completion of the dual result read. when a data transfer is complete and d out a and d out b hav e returned to three - state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cnvst low again. cnvst busy sclk t 2 t 1 t 3 serial read operation cs 1 12 t convert t quiet 06703-024 figure 22 . normal mode operation for the AD7366 busy sclk t 2 t 1 t 3 serial read operation cs 1 14 t convert t quiet 06703-025 cnvst figure 23 . normal mode operation for the ad7367
AD7366/ad7367 rev. d | page 21 of 28 shutd own mode shutdown mode is intended for use in applications where slow throughput rates are required. shutdown mode is suited to appli cations where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus , shutdown. when the AD7366/ad7367 are in full power - down, all analog circuitry is powered d own. t he falling edge of cnvst initiates the conversion. the busy output su bsequently goes high to indicate that the conversion is in progress. after the conversion is completed, the busy output returns low. if the cnvst signal is at logic low when busy goes low , the part enter s shut down at the end of the conver sion phase. while the part is in shut down mode , the digital output code from the last conversion on each adc can still be read from the d out pins. to read the d out data , cs must be brought low as described in the serial interface s ection. the d out pins return to three - state when cs is brought back to logic high. to exit full power - down and to power up the AD7366/ad7367 , a rising e dge of cnvst is required. after the required pow er - up time has elapsed, cnvst can be brought low again to initiate another conver sion, as shown in figure 24 (s ee th e power - up times section fo r power - up times associated with the AD7366/ ad7367 ). p ower -up t imes the AD7366/ad7367 ha ve one power - down mode, which is described in detail in the shutdown mode section . this section deals with the power - up time requir ed when comi ng out of shutdown mode . it should be n oted that the power - up time s (as explained in this section ) apply with the recommended capaci - tors in place on the d cap a and d cap b pins . to power up f rom shut down, cnvst must be brought high and remain high for a minimum of 70 s , as shown in figure 24. when power supplies are first applied to the AD7366/ad7367 , the adc can power up with cnvst in either the low or high logic state. before attempting a valid conversion , c nvst must be brought high and remain high for the recommended power - up time of 70 s . t hen cnvst can be brought low to initiate a conversion. with the AD7366 /ad7367 , no dummy conversion is required before valid data can be read from th e d out pins. t o place the part in shutdown mode when the supplies are first applied, the AD7366/ad7367 must be powered up and a conversion initiated . however, cnvst should remain in the logic low state so that when the busy signal goes l ow , the part enters shutdown. when supplies are applied to the AD7366/ad7367 , sufficient time must be allowed for any external reference to power up and to charge the various reference buffer decoupling capacitors to their final values . busy sclk serial read operation cs 1 12 t convert t 3 t 2 enters shutdown t power-up 06703-026 cnvst figure 24 . autoshutdown mode for the AD7366
AD7366/ad7367 rev. d | page 22 of 28 serial interface figure 25 a nd figure 26 show the detailed timing diagram fo r serial interfacing to the AD7366 and the ad7367 . on the fal ling edge of cnvst , the AD7366/ad7367 simultaneously convert t he selected channels. these conversions are performed using the on - chip oscillator. after the falling edge of cnvst , the busy signal goes high, indicating th at th e conver sion has started. the busy signal returns low when the conversion has been completed. the data can now be read from the d out pins. the cs and sclk signals are required to transfer data from the AD7366/ad7367 . the AD7366/ad7367 ha ve two ou tput pins correspo nding to each adc. data can be read from the AD7366/ ad7367 using both d out a and d out b . a lternatively , a single output pin of the users choice can be used. the sclk input signal provides the clock source for the serial interface. the cs goes low to access data from the AD7366/ad7367 . the falling edge of cs takes the bus out of three - state and clocks out the msb of the conversion result. the data stream consists of 12 bits of data for the ad736 6 and 14 b it s of data for the ad7367 , msb first. the first bit of the conversion result is valid on the first sclk falling edge after the cs fal ling edge. the subsequent 1 1 /1 3 bits of data for the AD7366/ad7367 , respectively , are clocked out on th e falling edge of the sclk signal. a minimum of 1 2 clock p ulses must be provided to the AD7366 to access each conversi on result, and a minimum of 14 clock p ulses must be provided to the ad7367 to access the conversion result. figur e 25 shows how a 12 sclk read is used to access the conversion results for the AD7366, and figure 26 illustrates the case for the ad7367 with a 14 sclk read. on the rising edge of cs the conversion is terminate d and d out a and d out b return to three - state. if cs is not brought high, but is instead held low for an additional 14 sclk cycles the data from the other dout pin follows on the selected dout pin. note, the second serial result from the ad 7366 is preceeded by two zeros. s ee figure 27 and figure 28 , where d out a is shown. in this case, the d out line in use returns to three - state on the rising edge of cs . if the falling e dge of sclk coincides with the falling edge of cs , the falling edge of sclk is not acknowledged by the AD7366/ ad7367, and the next falling edge of sclk is the first one registered after the falling edge of cs . the cs pin can be brought low be fore the busy signal goes low , indic at ing the end of a conversion. when cs is at a logic low state , the data bus is brought out o f three - state . this feature can be u s ed to ensure that the msb is va lid on the falling edge of busy by bring ing cs low a minimum of t 4 before the busy signal goes low. the dotted cs line in figure 22 and figure 23 illustrates this fea ture . alternatively, the cs pin can be tied to a low logic state continu - ously. in this case, the d out pins never enter three - state and the data bus is continuously active. under these conditions, the msb of the conversion result for the AD7366/ad736 7 is available on the falling edge of the busy signal. the next most significant bit is available on the first sclk falling edge after the busy signal has gone low. this mode of operation enables the user to read the msb as soon as it is made a vailable by the converter. d out a d out b three- state three-state cs sclk 1 5 12 2 3 4 db10 db11 db9 db8 db2 db1 db0 t 5 t 6 t 8 t 4 t 7 t 9 06703-027 figure 25 . serial interface timing d iagram for the AD7366 d out a d out b three- state three-state cs sclk 1 5 14 2 3 4 db12 db13 db 11 db10 db2 db1 db0 t 5 t 6 t 8 t 4 t 7 t 9 06703-028 figure 26 . serial interface timing diagram for the ad7367
AD7366/ad7367 rev. d | page 23 of 28 cs sclk 1 5 11 d out a three- state t 5 2 3 4 12 t 7 t 4 three- state t 8 t 6 10 db0 a 0 0 db11 b db1 a 13 14 26 db9 a db10 a db1 b db0 b db11 a 06703-030 figure 27 . reading data from both adcs on one d out li ne with 2 6 sclks for the AD7366 cs sclk 1 5 13 d out a three- state t 5 2 3 4 14 t 7 t 4 three- state t 8 t 6 12 db12 b db13 b db0 a db1 a 15 28 db 11 a db12 a db13 a db1 b db0 b 06703-029 figure 28 . reading data from both adcs on one d ou t line with 28 sclks for the ad7367
AD7366/ad7367 rev. d | page 24 of 28 microprocessor inter facing the serial interface on the AD7366/ad7367 allows the part s to be directly connected to a range of different microprocessors. this section explains how to interface the AD7366/ad7367 with some common microcontroller s and dsp serial interface protocols. AD7366/ad7367 to adsp - 218 x the adsp - 218x family of dsps interf ace s directly to the AD7366/ad7367 without any glue logic required. the v drive pin of the AD7366/ad7367 takes the same supply voltage as the power supply pin of the adsp - 218x. this allows the adc to operate at a higher supply voltage than its serial interf ace and therefore, the adsp - 218x , if necessary. this example shows both d out a and d out b of the AD7366/ad7367 connected to both serial ports of the adsp - 218x. the sport0 and sport1 control registers should be set up as shown in tab le 11 and table 12. table 11 . sport0 control register setup setting description tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right - justify data slen = 1111 16- bit data - word (or can be set to 1101 for 14 - bit data - word) isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 table 12 . sport1 control register setup setting description tfsw = rfsw = 1 alte rnate f raming invrfs = invtfs = 1 active low frame signal dtype = 00 right - justify data slen = 1111 16-b it data - word ( or can be set to 1101 for 14 - bit data - word) isclk = 0 e xternal serial clock tfsr = rfsr = 1 f rame every word irfs = 0 itfs = 1 t he connection diagram is shown in figure 29 . the adsp - 218x has the t fs0 and rfs0 of the sport0 and the rfs1 of sport1 tied together. tfs0 is set as an output, and both rfs0 and rfs1 are set as inputs. the dsp operates in alternate framing mode, and the sport control register is set up as described in table 11 and table 12 . the fr ame synchronization signal generated on the tfs is tied to cs . AD7366/ ad7367* sclk cs adsp-218x* *additional pins omitted for clarity. sclk0 dr0 rfs0 tfs0 d out a v drive v dd d out b dr1 rfs1 sclk1 irq busy cnvst flo 06703-031 figure 29 . interfacing the AD7366/ad7367 to the adsp - 218 x the AD7366/ad7367 busy line pr ovides an interrupt to the adsp - 218x when the conversion is complete. the conver - sion results can then be read from the AD7366/ad7367 using a read operation. when an interrupt is received on irq from the busy signal, a value is transmitted with tfs / dt ( adc control word). the tfs is used to control the rfs and, therefore , the reading of data. AD7366/ad7367 to adsp - bf53 x the adsp - bf53x family o f dsps interface s dir ectly to the AD7366/ad7367 without any glue logic required. the avail - ability of secondary receive registers on the serial ports of the blackfin ? dsps means that only one serial port is necessary to read from both the d out a and d out b p ins simultaneously. figure 30 shows both d out a and d out b of the AD7366/ad7367 connected to serial port 0 of the adsp - bf53x. the sport0 receive configuration 1 register and the sport0 receive configuration 2 register should be set up as outlined in table 13 and table 14. serial device a (primary) serial device b (secondary) AD7366/ ad7367* d out a cs sclk adsp-bf53x* *additiona l pins omitted for clarit y. dr0pri pf n rfs0 v drive v dd cnvst rclk0 rxints bus y dr0sec d out b sport0 06703-032 figure 30 . interfacing the AD7366/ad7367 to the adsp - bf53x
AD7366/ad7367 rev. d | page 25 of 28 table 13. sport0 receive configuration 1 register (sport0_rcr1) setting description rckfe = 1 sample data with falling edge of rsclk lrfs = 1 active low frame signal rfsr = 1 frame every word irfs = 1 internal rfs used rlsbit = 0 receive msb first rdtype = 00 zero fill irclk = 1 internal receive c lock rspen = 1 receive enabled slen = 1111 16- bit data - word (or can be set to 1101 for 14- bit data - word) tfsr = rfsr = 1 table 14. sport0 receive configuration 2 register (sport0_rcr2) setting description rxse = 1 secondary si de enabled slen = 1111 16- bit data - word ( or can be set to 1101 for 14- bit data - word) AD7366/ad7367 to tms320vc5506 the serial interface on the tms320vc5506 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7366/ad7367 . the cs input allows easy interfacing betw een the tms320vc5506 and the AD7366/ad7367 without any glue logic required. the serial ports of the tms320vc5506 are set up to operate in burst mode with internal clkx0 (t x serial clock on serial port 0) and fsx0 (t x frame sync from serial port 0). the serial port control (spc) registers must be set up as shown in table 15 . table 15 . seri al port control register setu p spc fo fsm mcm txm spc0 0 1 1 1 spc1 0 1 0 0 the connection diagram is shown in figure 31 . the v drive pin of the AD7366/ad7367 takes the same supply voltage as the power supply pin of the tms320vc5506 . this allows the adc to operate at a higher voltage than its serial interface and , therefore , the tms320vc5506 , if necessary. fsr1 fsr0 AD7366/ ad7367* sclk tms320vc5506* *additiona l pins omitted for clarit y. clkx0 dr1 clkr1 cl kx 1 d out b d out a v drive v dd cs fsx0 dr0 clkr0 intn xf cnvst bus y 06703-033 figure 31 . interfacing the AD7366/ad7367 to the tms320vc5506 as with the previous interfaces, conv ersion can be initiated from the tms320vc5506 or from an external source, and the processor is interrupted when the conversion sequence is completed. ad73 66/ad7367 to dsp563 xx the connection diagram in figure 32 shows how the ad73 66/ ad7367 can be con nected to the enhanced synchronous serial interface (essi ) of the dsp563xx family of dsps from motorola. there are two on - board essis, and each is operated in synchro - nous mode (bit syn = 1 in the crb register) with internally generate d word length frame sync for both t x and r x (bit fsl1 = 0 and bit fsl0 = 0 in the crb register ). normal operation of the essi is selected by sett ing mod = 0 in the crb register . set the word length to 16 by setting bit wl1 = 1 and bit wl0 = 0 in the cra register. the fsp bit in the crb register should be set to 1 so that the frame sync is negative.
AD7366/ad7367 rev. d | page 26 of 28 in th e example shown in figure 32 , the serial clock is taken from the essi0 , so the sc k0 pin must be set as an output ( sckd = 1) wh ile the sck1 pin is set as an input ( sckd = 0). the frame sync signal is taken from sc02 on essi0, so scd2 = 1 , while on essi1, scd2 = 0; therefore, sc12 is configured as an input. the v drive pin of the AD7366/ad7367 takes the same supply voltage as the po wer supply pin of the dsp563xx. this allows the adc to operate at a higher voltage than its serial interface and , therefore, the dsp563xx, if necessary. AD7366/ ad7367* sclk dsp563xx* *additiona l pins omitted for clarit y. sck0 sc12 srd1 srd0 cs d out a d out b v drive v dd sc02 sck1 irq n pb n cnvst bus y 06703-034 figure 32 . interfacing the AD7366/ad7367 to the dsp563xx
AD7366/ad7367 rev. d | page 27 of 28 application hin ts layout and grounding the printed circ uit board that houses the AD7366/ad7367 should be designed so that the analog and digital sections are confined to separate areas of the board. this design facilitates the use of ground planes that can be easily se parated. to provide optimum shielding for ground planes, a minimum etch technique is generally the best option . all agnd pins on the AD7366/ad7367 should be connected to the agnd plane. digital and analog ground pins should be joined in only one place. if the AD7366/ad7367 are in a system where multiple devices require an agnd and dgnd connection, the connec - tion should still be made at only one poin t. a star point should be established as close as possible to the ground pins on the AD7366/ad7367 . good co nnections should be made to the power and ground planes. this can be done with a single via or multiple vias for each supply and ground pin. avoid running digital lines under the AD7366/ad7367 device s because this couples noise onto the die. however, the analog ground plane should be allowed to run under the AD7366/ ad7367 to avoid noise coupling. the power supply lines to the AD7366/ad7367 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the pow er supply line. to avoid radiating noise to other sections of the board, com - ponents with fast switching signals, such as clocks, should be shielded with digital ground and should never be run near the analog inputs. avoid crossover of digital and analog signals. to reduce the effects of feedthrough within the board, traces should be run at right angles to each other. a microstrip technique is the best method, but its use may not be possible with a double - sided board. in the microstrip technique , the compo nent side of the board is dedicated to ground planes, and signals are placed on the other side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have a low effective series resistance (esr) and low effective series inductance ( esi), such as is typical of common ceramic and surface mount types of capacitors. these low esr, low esi capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
AD7366/ad7367 rev. d | page 28 of 28 outline dimension s 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 33 . 24 - lead thin shrink small outline package [tssop] (ru - 24) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7366bruz ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 AD7366bruz -r l7 ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 AD7366bruz - 500rl7 ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 ad7367b ruz ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 ad7367bruz - 500r l7 ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 ad7367bruz -r l7 ? 40 c to +85 c 24- lead thin shrink small outline package [tssop] ru -24 eva l- ad736 6 cbz evaluation board eval - ad7367 cbz evaluation board eval - control brd2 control board 1 z = rohs compliant part. ? 2007 - 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06703 -0- 11/10(d)

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